5-stage Pipelined Single Cycle Core

• Tech Stack: Chisel (Scala), Logisim, Assembly Language
• Github URL: Project Link

The project implements a pipelined single-cycle core processor using Chisel, a hardware descriptive language. The processor follows the RISC-V ISA and consists of five stages: fetch, decode, execute, data memory, and write-back.

Chisel is used to design and describe the processor's components, including the instruction fetch unit, decoder, ALU, control unit, multiplexers, and data memory. Assembly language is employed to write instructions in a 32-bit format compatible with the processor.

Logisim software is used to simulate and visualize the behavior of the designed pipelined processor. It provides a graphical interface to create and connect components, allowing for a comprehensive understanding of the processor's functionality and the flow of data through its stages.